STP=0, LSBF=0, RXDESEL=0, CPHA=0, CPOL=0, SINV=0, FM=0, BPEN=0, CHR=00, BLK=0, GM=0, MP=0, CKE=00, DEN=0, MOD=000
Common Control Register 3
| CPHA | Clock Phase Select 0 (0): Data is sampled at an odd edge and changes at an even edge. (Clock is delayed.) 1 (1): Data changes at an odd edge and is sampled at an even edge. (Clock is not delayed) |
| CPOL | Clock Polarity Select 0 (0): SCKn in idle state is 0. 1 (1): SCKn in idle state is 1. |
| BPEN | Synchronizer bypass enable 0 (0): Synchronizer circuit is not bypassed. 1 (1): Synchronizer circuit is bypassed. |
| CHR | Character Length 0 (00): Transmit/receive in 9-bit data length 1 (01): Transmit/receive in 9-bit data length 2 (10): Transmit/receive in 8-bit data length (initial value) 3 (11): Transmit/receive in 7-bit data length |
| LSBF | LSB First select 0 (0): MSB first 1 (1): LSB first |
| SINV | Transmitted/Received Data Invert 0 (0): TDR contents are transmitted to TSR as they are. RSR contents are stored to RDR as they are. 1 (1): TDR contents are inverted before being transmitted to TSR. RSR contents are inverted and stored to RDR. |
| STP | Stop Bit Length 0 (0): 1 stop bit / Break Delimiter length is 1bit 1 (1): 2 stop bits / Break Delimiter length is 2bits |
| RXDESEL | Asynchronous Start Bit Edge Detection Select 0 (0): The low level on the RXDn pin is detected as the start bit. 1 (1): A falling edge on the RXDn pin is detected as the start bit. |
| MOD | Communication mode select 0 (000): Asynchronous mode (Multi-processor mode) 1 (001): Smart card interface mode 2 (010): Clock synchronous mode 3 (011): Simple SPI mode 4 (100): Simple IIC mode 5 (101): Manchester mode 6 (110): Simple LIN mode 7 (111): Setting prohibited |
| MP | Multi-Processor Mode 0 (0): Multi-processor communications function is disabled 1 (1): Multi-processor communications function is enabled |
| FM | FIFO Mode select 0 (0): TDR register, RDR register is non-FIFO buffer configuration 1 (1): TDR register, RDR register is FIFO buffer configuration |
| DEN | Driver enable 0 (0): RS-485 Driver control function disable. 1 (1): RS-485 Driver control function enable. |
| CKE | Clock enable 0 (00): In the case of Asynchronous modeOn-chip baud rate generatorThe SCKn pin is available for use as an I/O port in accord with the I/O port settings. In the case of Manchester mode and Simple LIN modeOn-chip baud rate generatorThe SCKn pin functions as I/O port. In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Output disabled (The SCKn pin is available for use as an I/O port in accord with the I/O port settings.) In the case of Smart card interface mode and CCR3.GM = 1Output fixed low 1 (01): In the case of Asynchronous modeOn-chip baud rate generatorThe clock with the same frequency as the bit rate is output from the SCKn pin. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeInternal clock (Master operation)The SCKn pin functions as the clock output pin. In the case of Smart card interface mode and CCR3.GM = 0Clock output In the case of Smart card interface mode and CCR3.GM = 1Clock output 2 (10): In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Output fixed high 3 (11): In the case of Asynchronous modeExternal clock When using the external clock16 times the bit rate should be input from the SCKn pin when CCR2.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the CCR2.ABCS bit is 1. In the case of Manchester mode and Simple LIN modeProhibited In the case of Clock synchronous mode, Simple SPI modeExternal clock (Slave operation)The SCKn pin functions as the clock input pin. In the case of Smart card interface mode and CCR3.GM = 0Prohibited In the case of Smart card interface mode and CCR3.GM = 1Clock output |
| GM | GSM Mode 0 (0): Non-GSM mode operation 1 (1): GSM mode operation |
| BLK | Block Transfer Mode 0 (0): Non-block transfer mode operation 1 (1): Block transfer mode operation |